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QsNet II
QsNet II was the fourth and penultimate generation of Quadrics Interconnect family products. Quadrics QsNetII interfaced to the host computer through the standard IO PCI-X bus. Later versions of the card had PCIe physical interfaces although this was bridged on the card to PCI-X with a performance penalty. A native PCIe version was never developed. Instead resource was focused on QsNetII's successor QsNetIII which although completed was never released commercially.. ==Architecture== The architecture of the network interface has been developed to offload the entire task of interprocessor communication from the main processor, and to avoid the overhead of system calls for user process to user process messaging. QsNetII is designed for use within SMP systems — multiple, concurrent processes can utilise the network interface without any task switching overhead. A I/O processor offloads protocol handling from the main CPU. Local memory on the PCI card provides storage for buffers, translation tables and I/O adapter code. All the PCI bandwidth is available to data communication.
抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)』 ■ウィキペディアで「QsNet II」の詳細全文を読む
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